Hardware-accelerated 3×3 median filter SoC on Altera DE2 (Cyclone II) using Nios II CPU, Avalon-MM bus, and a pipelined sorting-network IP core — implemented in Verilog with Quartus II 13.0 SP1.

Pooyan Arcade synthesized on an Altera DE2-35 Dev Board.

Missile Command Arcade synthesized on an Altera DE2-35 Dev Board.

Crazy Kong Arcade synthesized on an Altera DE2-35 Dev Board.

Phoenix Arcade synthesized on an Altera DE2-35 Dev Board.

Xevious Arcade synthesized on an Altera DE2-35 Dev Board.

Time Pilot Arcade synthesized on an Altera DE2-35 Dev Board.

Galaga Arcade synthesized on an Altera DE2-35 Dev Board.

Missile Command Arcade synthesized on an Altera DE2-35 Dev Board.

Bagman Arcade synthesized on an Altera DE2-35 Dev Board.

Crazy Climber Arcade synthesized on an Altera DE2-35 Dev Board.

Burgertime Arcade synthesized on an Altera DE2-35 Dev Board.