feat(riscv): calculator demo + synth riscv-runtime CLI command#90
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avrabe wants to merge 1 commit intofeat/riscv-startup-mtvecfrom
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feat(riscv): calculator demo + synth riscv-runtime CLI command#90avrabe wants to merge 1 commit intofeat/riscv-startup-mtvecfrom
avrabe wants to merge 1 commit intofeat/riscv-startup-mtvecfrom
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Track B4 — closes the loop on the RISC-V toolchain by wiring the startup
+ linker generators behind a `synth riscv-runtime` CLI command, then
exercising the full pipeline end-to-end via the existing
`examples/calculator/calculator.wat`.
## CLI: `synth riscv-runtime`
New subcommand emits `startup.c` + `linker.ld` to a target directory:
```
synth riscv-runtime -o build/ \
--target rv32imac \
--flash-origin 0x0 \
--ram-origin 0x80000000 \
--linear-memory-size 65536 \
--stack-size 4096 \
[--enable-fpu]
```
Prints the cross-link command at the end:
```
riscv64-unknown-elf-gcc -nostartfiles -nostdlib -mabi=ilp32 -march=rv32imac \
-T build/linker.ld -o firmware.elf build/startup.c <synth.o>
```
Configurable knobs cover the variant (rv32i, rv32imac, rv32gc, rv64imac,
rv64gc), memory map (flash/ram origins, linear-memory size, stack size),
and FPU init.
## Calculator end-to-end demo
`tests/integration/riscv_calculator_demo.sh` exercises the complete
pipeline against `examples/calculator/calculator.wat` (5 functions:
add, subtract, multiply, divide, modulo):
1. Compile WAT → RV32IMAC ELF via `synth compile --backend riscv`.
2. Verify all 5 calculator symbols are present in the symbol table.
3. Generate `startup.c` + `linker.ld` via `synth riscv-runtime`.
4. (Optional, skipped when toolchain absent) Cross-link with
`riscv64-unknown-elf-gcc` to produce a bootable `firmware.elf`.
End-to-end demo passes on the dev host even without the cross-toolchain,
exercising every layer of the RISC-V stack we built in B1/B2/B3.
## CHANGELOG / README
* CHANGELOG entry under [Unreleased] documenting the entire RISC-V
feature increment plus the M7 hardening and AAPCS regalloc fixes
from PR #86.
* README tagline updated from "WebAssembly-to-ARM Cortex-M" to
"WebAssembly-to-ARM/RISC-V" to reflect the second target.
## Test summary
* All 98 RISC-V backend tests still pass.
* All workspace tests pass; clippy clean; fmt clean.
* `bash tests/integration/riscv_calculator_demo.sh` — 4/4 stages pass.
* `bash tests/integration/riscv_codegen_smoke.sh` — 4/4 modules pass.
## What's still out of scope (future work)
* i64 lowering for RV32 (register-pair arithmetic — analogue of the i64
ARM work landed in #86).
* RV32F/D float instructions.
* br_table jump-table emission.
* Cross-function calls + relocations for multi-function module linking.
* RISC-V Rocq proofs (deferred until the validator-pattern work lands;
see issue #76).
* Real-hardware validation on a HiFive1 / equivalent board.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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Track B4 — closes the loop on the RISC-V toolchain. Stacked on #89.
CLI: `synth riscv-runtime`
New subcommand that emits a complete RV32 build runtime:
```
synth riscv-runtime -o build/ \
--target rv32imac \
--flash-origin 0x0 \
--ram-origin 0x80000000 \
--linear-memory-size 65536 \
--stack-size 4096
```
Writes `startup.c` (reset vector + trap entry) and `linker.ld`. Prints the cross-link command at the end.
End-to-end calculator demo
`tests/integration/riscv_calculator_demo.sh` exercises the complete pipeline:
All 4 stages pass on the dev host.
CHANGELOG / README
🤖 Generated with Claude Code