feat(riscv): RV32IMAC backend skeleton — encoder, ELF builder, PMP allocator

[avrabe]

Track B1 deliverable — adds a parallel RISC-V code-generation path alongside the ARM backend. Stacked on top of #86 (M7 hardening + AAPCS fixes) so it carries those changes too. Once #86 merges, this rebases onto main as a clean diff of just the RISC-V additions.

What this PR adds

• New crate crates/synth-backend-riscv/ — registered as a --backend riscv option in the CLI.
• End-to-end pipeline working today: WASM `(add (param i32 i32) (result i32) local.get 0 local.get 1 i32.add)` → real RISC-V ELF (`file` reports "UCB RISC-V, RVC, soft-float ABI").

Modules

Module	What it does
`register.rs`	x0..x31 enum, ABI aliases (a0..a7, s0..s11, t0..t6), psABI callee-saved set
`riscv_op.rs`	RV32I + Zicsr + M-extension instruction enum, Branch/Csr typed wrappers
`encoder.rs`	R/I/S/B/U/J bit-packers, cross-checked against canonical reference encodings
`pmp.rs`	Physical Memory Protection allocator (RISC-V analogue of MPU). NAPOT for power-of-2, TOR fallback
`elf_builder.rs`	RV32 ELF emitter (EM_RISCV=0xF3, RVC e_flags), 2-pass label resolution
`selector.rs`	Skeleton WASM-to-RV32 lowering (i32 arith, params, return). Full parity = B2
`backend.rs`	`Backend` trait impl, registers as "riscv" with `produces_elf=true`

CLI integration

• New `riscv` feature in `synth-cli` (default-enabled).
• Compile path now dispatches to RISC-V ELF emission when `target_spec.family == ArchFamily::RiscV`, replacing the unconditional ARM ELF wrapper that was producing wrong-machine-type binaries.
• `synth backends` now lists "riscv" alongside "arm".

End-to-end demo

```
$ synth compile add.wat -o rv.elf --backend riscv --target riscv32imac
$ file rv.elf
rv.elf: ELF 32-bit LSB relocatable, UCB RISC-V, RVC, soft-float ABI

$ xxd -s 52 -l 20 rv.elf
9302 0500 # addi t0, a0, 0 (LocalGet 0)
1383 0500 # addi t1, a1, 0 (LocalGet 1)
b382 6200 # add t0, t0, t1
1385 0200 # addi a0, t0, 0
6780 0000 # ret (jalr zero, 0(ra))
```

Encoder cross-checks

The encoder tests use literal hex values that any toolchain (GCC, LLVM, official spec tables) must produce. Examples from the test suite:

• `addi a0, a0, 1` → `0x00150513`
• `auipc ra, 0` → `0x00000097`
• `csrrw zero, mtvec, a0` → `0x30551073`
• `mul a0, a0, a1` → `0x02b50533`
• `mret` → `0x30200073`
• `fence iorw,iorw` → `0x0FF0000F`

Test summary

• 60 new tests in synth-backend-riscv: encoder vectors, register file, PMP allocation, ELF round-trip, selector behavior, backend trait conformance.
• All 600+ existing workspace tests still pass — zero regressions.
• `cargo clippy --workspace --all-targets -- -D warnings` clean.
• `cargo fmt --check` clean.

What's deliberately out of scope (Tracks B2/B3/B4)

• Comparisons (lt_s/lt_u/gt_s/gt_u/le/ge/eq/ne)
• Loads / stores (i32.load, i32.store, ...)
• Division / remainder (encoded but not wired into the selector yet)
• i64 lowering (RV32 register pairs)
• Control flow (block / loop / if / br / br_table)
• Cross-function calls (jal + linker relocations)
• Trap handler / startup code (mtvec setup, mret)
• Renode RV32 platform + integration test (B2)
• Linker script generator (B3)
• RISC-V Rocq proofs (later)

🤖 Generated with Claude Code

[temper-pulseengine]

Automated review for PR #87

pulseengine/synth:feat/riscv-skeleton → pulseengine/synth:fix/synth-optimized-regalloc-params

Verdict: 💬 Comment

Summary: The pull request is approved. The changes enhance the RISC-V backend by adding support for building relocatable ELF files and multi-function ELF files. This allows for more flexible integration of the backend into various bare-metal environments.

Findings: 0 mechanical (rivet) · 1 from local AI model.

Findings (1):

1. crates/synth-backend-riscv/Cargo.toml:1

   [dependencies]
   

   The RISC-V backend has its own dependencies.

---

Generated by a local AI model and post-validated against a strict JSON contract. Each finding includes the verbatim line being criticised — verify by reading the file at the cited location.

Reviewed at 510b193