Add some RISC-V options#447
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| #define RISCV_HWCAP_D (UINT64_C(1) << ('D' - 'A')) | ||
| #define RISCV_HWCAP_Q (UINT64_C(1) << ('Q' - 'A')) | ||
| #define RISCV_HWCAP_C (UINT64_C(1) << ('C' - 'A')) | ||
| #define RISCV_HWCAP_B (UINT64_C(1) << ('B' - 'A')) |
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AFAIK HWCAP_B still not part of the linux kernel
ref:
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Also your PR do not contains any RISCV_B in the RiscvFeaturesEnum so it seems inconsistent imho
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Yes, I had had the same thought that maybe HWCAP_B should not be part of the PR. I’ll take it out and resubmit.
| LINE(RISCV_Zicsr, Zicsr, "_zicsr", 0, 0) \ | ||
| LINE(RISCV_Zifencei, Zifencei, "_zifencei", 0, 0) | ||
| LINE(RISCV_Zifencei, Zifencei, "_zifencei", 0, 0) \ | ||
| LINE(RISCV_Zfa, Zfa, "_zfa", 0, 0) \ |
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why not adding _zfbfmin ?
ref: https://elixir.bootlin.com/linux/v7.0.1/source/arch/riscv/kernel/cpufeature.c#L525
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I was influenced by which features are currently implemented by RISC-V chip vendors, but yes, Zfbfmin is optional in the RVA23 profile, so I ought to include it.
| LINE(RISCV_Zfhmin, Zfhmin, "_zfhmin", 0, 0) \ | ||
| LINE(RISCV_Zca, Zca, "_zca", 0, 0) \ | ||
| LINE(RISCV_Zcb, Zcb, "_zcb", 0, 0) \ | ||
| LINE(RISCV_Zcd, Zcd, "_zcd", 0, 0) \ |
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This adds the bit manipulation and half-precision floating point extensions