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enhancement

help wanted

Status: Open.

Task

#268 In SiLab-Bonn/basil;

· cbespin opened on May 5, 2026

Update Modules in Documentation

Status: Open.

Task

#267 In SiLab-Bonn/basil;

· rpartzsch opened on Apr 23, 2026

old bitarray version compatibility issue

Status: Open.

#249 In SiLab-Bonn/basil;

· fiene-weber opened on Dec 12, 2025

GPIO module does not work for sizes not equaling full bytes

Status: Open.

#245 In SiLab-Bonn/basil;

· cbespin opened on Nov 6, 2025

SiTCP 10G implementation

question

Status: Open.

#224 In SiLab-Bonn/basil;

· cbespin opened on May 14, 2024

pyserial not able to reinitialize MIO1.04 after first execution

Status: Open.

#204 In SiLab-Bonn/basil;

· dschuechter opened on Jul 25, 2023

Q: Initialization procedure

Status: Open.

#175 In SiLab-Bonn/basil;

· leloup314 opened on Mar 7, 2022

Q: Tune tlu

question

Status: Open.

#89 In SiLab-Bonn/basil;

· themperek opened on Jul 6, 2018

StdRegister offset

question

Status: Open.

#76 In SiLab-Bonn/basil;

· themperek opened on Dec 14, 2017

·  

3.0.0

SEQ_GEN changes output when changing the memory content when in idle

Status: Open.

#55 In SiLab-Bonn/basil;

· laborleben opened on May 24, 2016

·  

v2.4.4

TL.SiUart needs changes

enhancement

Status: Open.

#39 In SiLab-Bonn/basil;

· laborleben opened on Sep 23, 2015

·  

2.1.3

Virtual DDR FIFO (AXI)

enhancement

Status: Open.

#16 In SiLab-Bonn/basil;

· themperek opened on Mar 25, 2015