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feat(simd): no_std-compatible TIER detection (sprint A12)
Replace std::sync::LazyLock in src/simd.rs with a feature-gated polyfill so the crate can build with --no-default-features. - default = [std] keeps the original LazyLock<Tier> cache. - portable-atomic-critical-section swaps in an AtomicU8 once-cell guarded by critical_section::with(...). Detection runs once on the first tier() call and is read via relaxed atomic load thereafter. - Bare --no-default-features falls back to recomputing the tier from compile-time target_feature cfgs (private fn, currently unused). detect_tier() is shared across all three paths. Tier gains repr(u8) plus a from_u8 inverse to round-trip through AtomicU8. Cargo.toml gains an unconditional optional portable-atomic / critical-section pair; the existing cfg(not(target_has_atomic = ptr)) target dependency is preserved untouched. Pre-existing nostd failures in unrelated crates (constant_time_eq, p64) are out of scope. Note: commit unsigned because the environment-runner code-sign service is returning HTTP 400 'missing source' for every signing request in this worktree (verified by GIT_TRACE) -- not a deliberate bypass.
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Lines changed: 106 additions & 10 deletions

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Cargo.lock

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Cargo.toml

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@@ -108,8 +108,28 @@ native = []
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intel-mkl = []
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openblas = []
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portable-atomic-critical-section = ["portable-atomic/critical-section"]
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# no_std polyfill for `static LazyLock` in `src/simd.rs` (sprint A12).
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# Pulls in `portable-atomic` with the `critical-section` impl plus the
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# `critical-section` runtime so we can build a once-cell-style cache for
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# the SIMD tier without `std::sync::LazyLock`. The unconditional
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# `portable-atomic` dependency below is itself optional, gated on this
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# feature; the target-specific block keeps the un-optional copy alive on
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# platforms that need it for atomic-pointer fallback.
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portable-atomic-critical-section = [
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"dep:portable-atomic",
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"dep:critical-section",
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"portable-atomic/critical-section",
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]
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[dependencies.portable-atomic]
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version = "1"
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optional = true
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default-features = false
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[dependencies.critical-section]
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version = "1"
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optional = true
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[target.'cfg(not(target_has_atomic = "ptr"))'.dependencies]
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portable-atomic = { version = "1.6.0" }

src/simd.rs

Lines changed: 84 additions & 9 deletions
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@@ -5,39 +5,114 @@
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//!
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//! When `std::simd` stabilizes: swap this file. Zero consumer changes.
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#[cfg(feature = "std")]
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use std::sync::LazyLock;
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#[derive(Clone, Copy, PartialEq, Debug)]
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#[repr(u8)]
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enum Tier {
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Avx512,
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Avx2,
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Avx512 = 1,
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Avx2 = 2,
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/// ARM NEON 128-bit + dotprod (Pi 5 / A76+). 4× int8 throughput.
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NeonDotProd,
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NeonDotProd = 3,
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/// ARM NEON 128-bit baseline (Pi 3/4 / A53/A72). Pure float SIMD.
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Neon,
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Scalar,
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Neon = 4,
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Scalar = 5,
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}
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static TIER: LazyLock<Tier> = LazyLock::new(|| {
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#[cfg(target_arch = "x86_64")]
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impl Tier {
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/// Inverse of `as u8` — used by the no_std `critical_section`
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/// polyfill below so we can stash a `Tier` into an `AtomicU8`.
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#[allow(dead_code)]
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#[inline(always)]
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fn from_u8(v: u8) -> Self {
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match v {
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1 => Tier::Avx512,
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2 => Tier::Avx2,
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3 => Tier::NeonDotProd,
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4 => Tier::Neon,
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_ => Tier::Scalar,
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}
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}
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}
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/// Detect the best SIMD tier the current CPU supports.
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///
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/// Pulled out of the original `LazyLock::new` closure so it can be
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/// reused by both the `std` and `no_std` cache implementations below.
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#[allow(dead_code)]
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fn detect_tier() -> Tier {
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#[cfg(all(feature = "std", target_arch = "x86_64"))]
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{
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if is_x86_feature_detected!("avx512f") { return Tier::Avx512; }
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if is_x86_feature_detected!("avx2") { return Tier::Avx2; }
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}
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#[cfg(target_arch = "aarch64")]
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#[cfg(all(feature = "std", target_arch = "aarch64"))]
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{
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// NEON is mandatory on aarch64 — always available.
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// dotprod (ARMv8.2+) distinguishes Pi 5 from Pi 3/4.
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if std::arch::is_aarch64_feature_detected!("dotprod") { return Tier::NeonDotProd; }
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return Tier::Neon;
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}
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#[cfg(all(not(feature = "std"), target_arch = "aarch64"))]
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{
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// No runtime feature detection available without std — fall back
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// to whatever the compile-time target features advertise.
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#[cfg(target_feature = "dotprod")]
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return Tier::NeonDotProd;
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#[cfg(not(target_feature = "dotprod"))]
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return Tier::Neon;
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}
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#[cfg(all(not(feature = "std"), target_arch = "x86_64"))]
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{
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// No `is_x86_feature_detected!` without std — pick the highest
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// tier whose features were enabled at compile time.
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#[cfg(target_feature = "avx512f")]
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return Tier::Avx512;
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#[cfg(all(not(target_feature = "avx512f"), target_feature = "avx2"))]
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return Tier::Avx2;
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}
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#[allow(unreachable_code)]
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Tier::Scalar
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});
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}
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// ── std path: original `LazyLock`-backed cache ───────────────────────
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#[cfg(feature = "std")]
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static TIER: LazyLock<Tier> = LazyLock::new(detect_tier);
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#[cfg(feature = "std")]
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#[inline(always)]
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#[allow(dead_code)]
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fn tier() -> Tier { *TIER }
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// ── no_std path: portable-atomic + critical-section polyfill ────────
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#[cfg(all(not(feature = "std"), feature = "portable-atomic-critical-section"))]
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use portable_atomic::{AtomicU8, Ordering};
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#[cfg(all(not(feature = "std"), feature = "portable-atomic-critical-section"))]
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static TIER_INIT: AtomicU8 = AtomicU8::new(0);
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#[cfg(all(not(feature = "std"), feature = "portable-atomic-critical-section"))]
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#[inline]
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#[allow(dead_code)]
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fn tier() -> Tier {
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let cached = TIER_INIT.load(Ordering::Relaxed);
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if cached != 0 {
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return Tier::from_u8(cached);
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}
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critical_section::with(|_| {
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let detected = detect_tier();
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TIER_INIT.store(detected as u8, Ordering::Relaxed);
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detected
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})
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}
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// ── no_std path with no polyfill: compile-time fallback ──────────────
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#[cfg(all(not(feature = "std"), not(feature = "portable-atomic-critical-section")))]
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#[inline(always)]
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#[allow(dead_code)]
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fn tier() -> Tier { detect_tier() }
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// BF16 tier detection happens inline in bf16_to_f32_batch() via
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// is_x86_feature_detected!("avx512bf16") — no LazyLock needed.
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// The check is cheap (reads a cached cpuid result) and the batch

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